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CY2275A
Pentium(R)/II Clock Synthesizer/Driver for Desktop PCs with Intel 82440LX with 3 DIMMs
Features
* Mixed 2.5V and 3.3V operation * Clock solution to meet requirements of Pentium(R) and Pentium(R) II motherboards -- Four CPU clocks at 2.5V -- Up to twelve 3.3V SDRAM clocks -- Seven synchronous PCI clocks -- Two 2.5V IOAPIC clocks at 14.318 MHz -- One 3.3V Ref. clock at 14.318 MHz * 1 ns-5.8 ns CPU-PCI delay, factory-EPROM programmable * I2CTM Serial Configuration Interface * Factory-EPROM programmable output drive and slew rate for EMI cusomization * Factory-EPROM programmable CPU clock frequencies for custom configurations * Powerdown, CPU stop and PCI stop pins for power management * High drive, low skew (<250ps) and low jitter outputs * Intel Test Mode support * Available in space-saving 48-pin SSOP package One of the PCI clocks is free-running. Additionally, the part outputs twelve 3.3V SDRAM clocks, two 2.5V IOAPIC clocks at 14.318 MHz, and one 3.3V reference clock at 14.318 MHz. The part has power-down, CPU stop, and PCI stop pins for power management control. These inputs are multiplexed with SDRAM clock outputs, and are selected when the MODE pin is driven LOW. Additionally, these inputs are synchronized on-chip, enabling glitch-free output transitions. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. Finally, when the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2275A outputs are designed for low EMI emission. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
T
CY2275A Selector Guide
Clocks Outputs CPU@2.5V (66.6MHz) SDRAM PCI (33.3MHz) IOAPIC (14.318 MHz) Ref (14.318MHz) CPU-PCI delay
Note: 1. One free-running PCI clock.
-12 4 9/12 7[1] 2 1 1-5.8 ns
Functional Description
The CY2275A is a Clock Synthesizer/Driver for a Pentium and Pentium II-based PCs using an Intel 82440LX or similar core-logic chipset. The CY2275A outputs four CPU clocks at 2.5V. There are seven PCI clocks, running at one half the CPU clock frequency.
Logic Block Diagram
VDDQ2 XTALIN
XTALOUT
Pin Configuration
IOAPIC [0:1] (14.318 MHz)
AVDD REF0 VSS XTALIN CPU PLL STOP LOGIC
Top View SSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 CY2275A-12 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 IOAPIC0 IOAPIC1 VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5/PWR_DWN VDDQ3 SDRAM6/CPU_STOP SDRAM7/PCI_STOP VSS OE MODE
REF0 (14.318 MHz)
14.318 MHz OSC.
CPUCLK [0-3] VDDCPU
XTALOUT VDDQ3 PCICLK_F PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDQ3
OE MODE
SDRAM5/PWR_DWN SDRAM [0-4],[8-11] SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
/2 Delay STOP LOGIC
PCICLK5 VSS SDRAM11 SDRAM10
PCI [0-5] PCICLK_F
VDDQ3 SDRAM9 SDRAM8 VSS SDATA SCLK
SCLK SDATA
SERIAL INTERFACE CONTROL LOGIC
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 October 12, 1998
CY2275A
Pin Summary
Name VDDQ3 VDDQ2 VDDCPU AVDD VSS XTALIN[2] XTALOUT
[2]
Pins 6, 14, 19, 30, 36 48 42 1 3, 9, 16, 22, 27, 33, 39, 45 4 5 28 29 31
Description 3.3V Digital voltage supply IOAPIC Digital voltage supply, 2.5V CPU Digital voltage supply, 2.5V Analog voltage supply, 3.3V Ground Reference crystal input Reference crystal feedback SDRAM clock output. Also, active LOW control input to stop PCI clocks, enabled when MODE is LOW. SDRAM clock output. Also, active LOW control input to stop CPU clocks, enabled when MODE is LOW. SDRAM clock output. Also, active LOW control input to power down device, enabled when MODE is LOW. SDRAM clock outputs Active HIGH Output Enable Input (see table below) CPU clock outputs PCI clock outputs, at one-half the CPU frequency Free-running PCI clock output IOAPIC clock output Reference clock outputs, 14.318 MHz, drives 45 pF load Serial data input for serial configuration port Serial clock input for serial configuration port Mode Select pin for enabling power management features
SDRAM7/ PCI_STOP SDRAM6/ CPU_STOP SDRAM5/ PWR_DWN
SDRAM[0:4],[8:11] 38, 37, 35, 34, 32, 21, 20, 18, 17 OE CPUCLK[0:3] PCICLK[0:5] PCICLK_F IOAPIC[0:1] REF0 SDATA SCLK MODE 26 44, 43, 41, 40 8, 10, 11, 12, 13, 15 7 47, 46 2 23 24 25
Note: 2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Function Table
OE 0 1 XTALIN 14.318 MHz 14.318 MHz CPUCLK[0:3] SDRAM[0:11] Hi-Z 66.67 MHz PCICLK[0:5] PCICLK_F Hi-Z 33.33 MHz REF0 IOAPIC[0:1] Hi-Z 14.318 MHz
Actual Clock Frequency Values
Clock Output CPUCLK Target Frequency (MHz) 66.67 Actual Frequency (MHz) 66.654 PPM -195
CPU and PCI Clock Driver Strengths
* Matched impedances on both rising and falling edges on the output drivers * Output impedance: 25 (typical) measured at 1.5V.
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CY2275A
Power Management Logic - Active when MODE pin is held `LOW'
CPU_STOP X 0 0 1 1 PCI_STOP X 0 1 0 1 PWR_DWN 0 1 1 1 1 CPUCLK Low Low Low 66/60 MHz 66/60 MHz PCICLK Low Low 33/30 MHz Low 33/30 MHz PCICLK_F Stopped Running Running Running Running Other Clocks Stopped Running Running Running Running Osc. Off Running Running Running Running PLLs Off Running Running Running Running
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits should be programmed to "0". * I2C Address for the CY2275 is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ----
Byte 0: Functional and Frequency Select Clock Register (1 = Enable, 0 = Disable)
Bit Pin # Description (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' Bit 1 1 1 0 0 Bit 0 1 - Three-State 0 - N/A 1 - Testmode 0 - Normal Operation Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 -Bit 2 -Bit 1 -Bit 0
Select Functions
Outputs Functional Description Three-State Test Mode CPU Hi-Z TCLK/2
[3]
PCI, PCI_F Hi-Z TCLK/4
SDRAM Hi-Z TCLK/2
Ref Hi-Z TCLK
IOAPIC Hi-Z TCLK
Note: 3. TCLK supplied on the XTALIN pin in Test Mode.
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CY2275A
Byte 1: CPU Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A N/A 40 41 43 44 Description (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' Not used - drive to `0' CPUCLK3 (Active/Inactive) CPUCLK2 (Active/Inactive) CPUCLK1 (Active/Inactive) CPUCLK0 (Active/Inactive)
Byte 2: PCI Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -7 15 14 12 11 10 8 Pin # Description (Reserved) drive to `0' PCICLK_F (Active/Inactive) PCICLK5 (Active/Inactive) PCICLK4 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive) PCICLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 28 Bit 6 29 Bit 5 31 Bit 4 32 Bit 3 34 Bit 2 35 Bit 1 37 Bit 0 38
Byte 4: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A N/A 17 18 20 21 Description Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' SDRAM11 SDRAM10 SDRAM9 SDRAM8
Byte 5: Peripheral Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A 46 47 N/A N/A N/A 2 Description (Reserved) drive to `0' (Reserved) drive to `0' IOAPIC1 (Active/Inactive) IOAPIC0 (Active/Inactive) (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' REF0 (Active/Inactive)
Byte 6: Reserved, for future use
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CY2275A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ....................... +260C Junction Temperature ................................................ +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[4]
Parameter AVDD, V DDQ3 VDDCPU VDDQ2 TA CL CPU Supply Voltage IOAPIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK, IOAPIC[0:1] PCICLK, SDRAM REF0 Reference Frequency, Oscillator Nominal Value Description Analog and Digital Supply Voltage Min. 3.135 2.375 2.375 0 10 30, 20 20 14.318 Max. 3.465 2.9 2.9 70 20 30 45 14.318 MHz Unit V V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage Except Crystal Inputs Except Crystal Inputs I C inputs only IOH = 16 mA CPUCLK IOH = 18 mA IOAPIC Low-level Output Voltage VDDCPU = VDDQ2 = 2.375V IOL = 27 mA CPUCLK IOL = 29 mA IOAPIC High-level Output Voltage VDDQ3, AV DD = 3.135V IOH = 36 mA SDRAM IOH = 32 mA PCICLK IOH = 36 mA REF0 VOL Low-level Output Voltage VDDQ3, AV DD = 3.135V IOL = 29 mA SDRAM IOL = 26 mA PCICLK IOL = 29 mA REF0 IIH IIL IOZ IDD IDD IDDS Input High Current Input Low Current Output Leakage Current Power Supply Current[5] Power Supply Current[5] Power-down Current VIH = VDD VIL = 0V Three-state VDD = 3.465V, VIN = 0 or V DD, Loaded Outputs, CPU clocks = 66.67 MHz VDD = 3.465V, VIN = 0 or V DD, Unloaded Outputs Current draw in power-down state -10 -10 +10 10 +10 300 120 500 A A A mA mA A 0.4V V 2.4 V 0.4 V 2.0
2
Test Conditions
Min. Max. Unit 2.0 0.8 0.7 V V V V
High-level Output Voltage VDDCPU = VDDQ2 = 2.375V
Notes: 4. Electrical parameters are guaranteed with these operating conditions. 5. Power supply current will vary with number of outputs which are running.
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CY2275A
Switching Characteristics[6]
Parameter t1 t1C t1C t1D t1D t2 Output All CPUCLK PCICLK CPUCLK PCICLK CPUCLK, IOAPIC PCICLK, REF0 SDRAM CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK, SDRAM PCICLK CPUCLK, PCICLK, SDRAM Description Output Duty Cycle
[7]
Test Conditions t1 = t1A / t1B Above 2.0V, 66.6 MHz, VDDCPU = 2.5V Above 2.4V, 33.3 MHz Below 0.4V, 66.6 MHz, VDDCPU = 2.5V Below 0.4V, 33.3 MHz Between 0.4V and 2.0V
Min. 45 5.2 12.0 5.0 12.0 0.75
Typ. 50
Max. 55
Unit % ns ns ns ns
CPU Clock HIGH Time PCI Clock HIGH Time CPU Clock LOW Time PCI Clock LOW Time CPU and IOAPIC Clock Rising and Falling Edge Rate PCI, REF0 Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
1
4.0
V/ns
t2 t2 t3 t4 t5 t6 t7 t8 t8 t9
Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 2.0V and 0.4V, VDDCPU = 2.5V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.5V CPU, PCI, and SDRAM clock stabilization from power-up
0.75 0.75 0.4 0.4
1 1
4.0 4.0 2.13 2.13
V/ns V/ns ns ns ps ns ps ps ps ms
100 1.0 3.5 500
250 5.8 600 250 500 3
Notes: 6. All parameters specified with loaded outputs. 7. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.
6
CY2275A
Timing Requirement for the I2C Bus
Parameter t10 t11 t12 t13 t14 t15 t16 SCLK Clock Frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period the first clock pulse is generated. The LOW period of the clock. The HIGH period of the clock. Setup time for start condition. (Only relevant for a repeated start condition.) Hold time DATA for CBUS compatible masters. for I2C devices DATA input set-up time Rise time of both SDATA and SCLK inputs Fall time of both SDATA and SCLK inputs Set-up time for stop condition 4.0 Description Min. 0 4.7 4 4.7 4 4.7 5 0 250 1 300 ns s ns s Max. 100 Unit kHz s s s s s s
t17 t18 t19 t20
Switching Waveforms
Duty Cycle Timing
t1A t1B
CPUCLK Outputs HIGH/LOW Time
t1C VDD OUTPUT 0V
t1D
All Outputs Rise/Fall Time
VDD OUTPUT 0V t2 t3 t2 t4
CPU-CPU Clock Skew
CPUCLK
CPUCLK t5
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CY2275A
Switching Waveforms (continued)
CPU-SDRAM Clock Skew
CPUCLK
SDRAM t7
CPU-PCI Clock Skew
CPUCLK
PCICLK t6
CPU_STOP [8, 9]
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External)
PCI_STOP [10, 11]
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) Notes: 8. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 9. CPU_STOP may be applied asynchronously. It is synchronized internally. 10. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 11. PCI_STOP may be applied asynchronously. It is synchronized internally.
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CY2275A
Switching Waveforms (continued)
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN# CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Timing Requirements for the I2C Bus
SDA
t11 SCL t12 t13
t18
t19
t12
t16
t14
t17
t15
t20
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CY2275A
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > R trace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F-22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
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CY2275A
Test Circuit
VDDQ3
1 0.1 F 3
48 0.1 F 45
VDDQ2
6 0.1 F 9 39 14 0.1 F 42 0.1 F VDDCPU
36
0.1 F
16
33 30 0.1 F 27
0.1 F
19
22
OUTPUTS CLOAD
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code CY2275APVC-12 Document #: 38-00613-D Package Name O48 Package Type 48-Pin SSOP Operating Range Commercial
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CY2275A
Package Diagram
48-Lead Shrunk Small Outline Package O48
51-85061-B
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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